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1 programmable v com calibrator with eeprom ISL24201 the ISL24201 provides an 8-bit programmable current sink that is used in conjunction with an ex ternal voltage divider and buffer amplifier to generate a voltage so urce that is positioned between the analog supply voltage and ground. the current sink?s resolution is controlled by an external resistor, r set , and the span of the v com voltage is controlled by the voltage divider resistor ratio and the source impedance of r 1 and r 2 . this device has an 8-bit data register and 8-bit eeprom for storing a volatile and a permanent value for its output. the ISL24201 has an i 2 c bus interface that is used to read and write to its registers and eeprom. at power-up the eeprom value is transferred to the data register and output. the ISL24201 is available in an 8 ld 3mm x 3mm tdfn package. this package has a maximum height of 0.8mm for very low profile designs. the ambient operating temperature range is -40c to +85c . features ? 8-bit, 256-step, adjustable sink current output ? 4.5v to 18v analog supply voltage operating range ? 2.25v to 3.6v logic supply voltage operating range ? 400khz, i 2 c interface ? on-chip 8-bit eeprom ? output guaranteed monotonic over-temperature ? pb-free (rohs-compliant) applications ?lcd panel v com generator ? electrophoretic display v com generator ? resistive sensor driver ? low power current loop related literature ? see an1621 for ISL24201 evaluation board application note ?ISL24201irtz-evalz evaluation board user guide? typical application micro- controller ISL24201 scl sda wp out set 3.3v v dd a vdd 8 5 4 3 7 6 1 2 r set r 1 r 2 lcd panel v com i 2 c port i/o pin el5411t figure 1. application showing ISL24201 with a buffer amplifier december 9, 2010 fn7586.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2010. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL24201 2 fn7586.1 december 9, 2010 block diagram pin configuration ISL24201 (8 ld tdfn) top view figure 2. block diagram of the ISL24201 gnd i 2 c interface dac registers analog dcp and current sink 8-bit eeprom scl sda wp v dd a vdd out set 1 8 2 5 7 6 3 4 ISL24201 current sink q1 a1 out a vdd wp gnd 1 2 3 4 8 7 6 5 set scl sda v dd pad (thermal pad connects to gnd) pin descriptions pin name pin number function out 1 adjustable sink current output pin. the current sunk into the out pin is equal to the dac setting times the maximum adjustable sink current divided by 256. see the ?set? pin function description below (pin 8) for the maximum adjustable sink current setting. a vdd 2 high-voltage analog supply. bypass to gnd with 0.1f capacitor. wp 3 eeprom write protect. active low. 0 = programming disabled; 1 = programming allowed. this pin has an internal pull-down current sink gnd 4 ground connection. v dd 5 system power supply input. bypass to gnd with 0.1f capacitor. sda 6 i 2 c serial data input and output scl 7 i 2 c clock input set 8 maximum sink current adjustment point. connect a resistor from set to gnd to set the maximum adjustable sink current of the out pin. the maximum adjustable sink current is equal to (a vdd /20) divided by r set . pad - thermal pad should be connected to system ground plane to optimi ze thermal performance.
ISL24201 3 fn7586.1 december 9, 2010 ordering information part number (notes 1, 2, 3) part marking interface temp range (c) package (pb-free) pkg. dwg. # ISL24201irtz 201z i 2 c -40 to +85 8 ld 3x3 tdfn l8.3x3a ISL24201irtz-evalz evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page ISL24201 . for more information on msl please see techbrief tb363 .
ISL24201 4 fn7586.1 december 9, 2010 absolute maximum rating s thermal information supply voltage a vdd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4v input voltage with respect to ground set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4v scl, sda and wp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v dd +0.3v output voltage with respect to ground out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a vdd continuous output current out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma esd ratings human body model (tested per jesd22-a114) . . . . . . . . . . . . . . . . . 7kv machine model (tested per jesd22-a115). . . . . . . . . . . . . . . . . . . . 250v charged device model (tested per jesd22-c101). . . . . . . . . . . . . .1.5kv latch up (tested per jesd 78, class ii, level a). . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 8 ld tdfn package (notes 4, 5). . . . . . . . . 53 11 moisture sensitivity (see technical brief tb363) all packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . level 1 maximum die temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions operating range a vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 19v v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25v to 3.6v ambient operating temperature . . . . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications test conditions: v dd = 3.3v, a vdd = 18v, r set = 5k , r 1 = 10k , r 2 = 10k , (see figure 5); unless otherwise specified. typicals are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c . symbol parameter test conditions min (note 6) typ max (note 6) units dc characteristics v dd v dd supply range - operating 2.25 3.6 v a vdd a vdd supply range supporting eeprom programming 10.8 19 v a vdd a vdd supply range for wide-supply operation (not supporting eeprom programming) 4.5 19 v i dd v dd supply current wp = scl = sda = v dd 37 65 a i avdd a vdd supply current wp = scl = sda = v dd 24 38 a out characteristics set zse set zero-scale error 3 lsb set fse set full-scale error 8 lsb v out out voltage range i out < 0.5ma v set + 0.4 a vdd v set vd set voltage drift 7 v/c i out maximum out sink current 4ma inl integral non-linearity 2 lsb dnl differential non-linearity 1 lsb i 2 c inputs and output i 2 cv ih sda, scl logic 1 input voltage 1.44 v i 2 cv il sda, scl logic 0 input voltage 0.55 v i 2 c h sda, scl hysteresis 260 mv i l input leakage current of sda, scl 1 a vol s sda output logic low i = -3ma 0.4 v v ih wp input logic high 0.7v dd v v il wp input logic low 0.3v dd v v wp h wp input hysteresis 260 mv il w p n wp input leakage current -0.20 -0.5 -1 a
ISL24201 5 fn7586.1 december 9, 2010 application information the ISL24201 provides the ability to adjust the v com voltage during production test and alignm ent, under digital control, to minimize the flicker of an lcd panel. a digitally controlled potentiometer (dcp), with 256 steps of resolution, adjusts the sink current of the out pin. figure 3 shows the v com adjustment using a mechanical potentiometer circ uit and the equivalent circuit replacement with the ISL24201. the output is connected to an external voltage divider, as shown in figure 3, so that the ISL24201 will have the ability to reduce the voltage on the output by increasi ng the out pin sink current. the amount of current sunk is controlled by the i 2 c serial interface. i 2 c timing f clk i 2 c clock frequency 400 khz t sch i 2 c clock high time 0.6 s t scl i 2 c clock low time 1.3 s t dsp i 2 c spike rejection filter pulse width 050 ns t sds i 2 c data set up time 250 ns t sdh i 2 c data hold time 250 ns t buf i 2 c time between stop and start 200 s t sts i 2 c repeated start condition set-up 0.6 s t sth i 2 c repeated start condition hold 0.6 s t sps i 2 c stop condition set-up 0.6 s c sda sda pin capacitance 10 pf c s scl pin capacitance 10 pf t w eeprom write cycle time 100 ms note: 6. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. electrical specifications test conditions: v dd = 3.3v, a vdd = 18v, r set = 5k , r 1 = 10k , r 2 = 10k , (see figure 5); unless otherwise specified. typicals are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c . (continued) symbol parameter test conditions min (note 6) typ max (note 6) units out set ISL24201 or isl24202 r 1 r 2 a vdd a vdd v com i out v dd r set r a r c a vdd v com r b r 1 = r a r 2 = r b +r c r set = r a r b + r a r c 20r b figure 3. mechanical adjustment replacement
ISL24201 6 fn7586.1 december 9, 2010 dcp (digitally controlled potentiometer) figure 4 shows the relationship between the register value and the resistor string of the dcp. note that the register value of zero actually selects the first step of the resistor string. the output voltage of the dcp is given by equation 1: output current sink figure 5 shows the schematic of the out pin current sink. the circuit made up of amplifier a1 , transistor q1, and resistor r set forms a voltage controlled current source. the external r set resistor sets the full-scale sink current that determines the lowest output voltag e of the external voltage divider r 1 and r 2 . i out is calculated as shown by equation 2: the maximum value of i out can be calculated by substituting the maximum register value of 255 into equation 2, resulting in equation 3: equation 2 can also be used to calculate the unit sink current step size by removing the register value term from it as shown in equation 4. the voltage difference between the out pin and set pin, which are also the drain and source of the ou tput transistor, should be greater than the minimum saturation voltage for the i out(max) being used. this will keep the outp ut transistor in its saturation region to maintain linear operation over the full range of register values. figure 6 shows i ds vs v ds for transistor q1. the line labeled "minimum saturation voltage" is the minimum voltage that should be maintained across the drain and source of q1. to find the minimum saturation voltage for a specific condition, locate the voltage at the intersection of the i out(max) value from equation 3 and the line labeled "minimum saturation voltage". v dcp registervalue 1 + 256 -------------------------------------------------- - ?? ?? a vdd 20 ------------- - ?? ?? = (eq. 1) a vdd 19r r 0 1 2 255 254 253 252 251 register value a vdd 20 v dcp figure 4. simplified sche matic of digital control potentiometer (dcp) a vdd r set v dcp set out a vdd i out r 1 r 2 v sat v set = (i out )*(r set ) = v dcp q1 a1 v out figure 5. current sink circuit i out v dcp r set ------------- registervalue 1 + 256 -------------------------------------------------- - ?? ?? a vdd 20 ------------- - ?? ?? 1 r set ------------ - ?? ?? == (eq. 2) i out max () a vdd 20r set -------------------- = (eq. 3) i step a vdd 256 () 20 () r set () --------------------------------------------- - = (eq. 4) figure 6. i ds vs v ds for the ISL24201 output transistor 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 012345678910 vds (v) saturation region ids (ma) minimum saturation voltage
ISL24201 7 fn7586.1 december 9, 2010 the maximum voltage on the set pin is a vdd /20 and is added to the minimum voltage difference between the v out and set pins to calculate the minimum v out voltage, as shown in equation 5. output voltage the output voltage, v out , of the out pin can be calculated from equation 6: while equation 6 can be used to calculate the output voltage, it does not help select the values of r 1 , r 2 and r set to obtain a specific range of v com voltages. output voltage span calculation the span of the output voltage is typically centered around the nominal v com voltage value, which is typically near half of the a vdd voltage. the high v com voltage occurs with the register value of zero, while the low v com voltage occurs with the register value of 255. figure 7 shows the de finition of several terms used later in the text. there are three variables that control the v com calibrator?s operating point; the span of the v com voltage, the maximum current sink and the source impe dance of the resistive divider. figure 8 shows a range of operating points for these three variables and a quick way to estimate a specific operating point. the x-axis is the span of the v com voltage (high v com voltage - low v com voltage), and the y-axis is the maximum sink current set by r set . the individual plots of each r th show the v com span plotted against the maximum out sink current given that value of source impedance of the voltage divider. r th is the thevenin equivalent resistance of the voltage divider r 1 and r 2 , which is the resistance of the parallel combination of r 1 and r 2 , as shown in equation 7. the span of the v com voltage is shown by equation 8. to make a final selection of the resistor values for r 1 and r 2 , the supply voltage a vdd and the value of r set are specified. the calculations for r 1 and r 2 are shown in equations 9 and 10: the r 1 and r 2 calculations are based on the span of the v com voltage being centered at half the a vdd voltage. as an example, a vdd = 15v, the maximum value for i set is selected to be 100a and the required span is 2v. using figure 8 as a guide, the v com maximum is equal to 8.5v and the v com minimum is equal to 6.5v. rearranging equation and calculation the value of r set : calculating the value of r 1 is shown in equation 12. calculating the value of r 2 is shown in equation 13. v out min () a vdd 20 ------------- - minimumsaturationvoltage + (eq. 5 ) v out a vdd r 2 r 1 r 2 + -------------------- ?? ?? ?? 1 registervalue 1 + 256 -------------------------------------------------- - r 1 20r set -------------------- ?? ?? ?? ? ?? ?? ?? = (eq. 6) gnd a vdd nominal v com voltage high v com voltage low v com voltage span figure 7. voltage levels for v com r th r 1 r 2 r 1 r 2 + -------------------- = (eq. 7 ) v com span i set r th () = (eq. 8 ) figure 8. graph of v com span vs maximum outcurrent and r th 0.6 0.5 0.4 0.3 0.2 0.1 0 0123456 v com span (v) out pin maximum current (ma) r t h = 1 0 k r t h = 2 5 k r t h = 5 0 k r t h = 1 0 0 k r 1 40r set span () a vdd span + ----------------------------------------- - = (eq. 9 ) r 2 40r set span () a vdd span ? ----------------------------------------- - = (eq. 10) r set a vdd 20i out max () ------------------------------------ - 15 20 0.000100 () ------------------------------------- - 7500 == = (eq. 11) r 1 40 7500 () 2 () 15 2 + ---------------------------------- - 39.29k == (eq. 12) r 2 40 7500 () 2 () 15 2 ? ---------------------------------- - 46.15k == (eq. 13)
ISL24201 8 fn7586.1 december 9, 2010 table 1 shows the calculated results of the v com voltage with these values. figure 6 is used to find the minimum saturation voltage for an i out maximum of 100a, which is about 0.3v. the minimum v out is 6.5v, which also meets the minimum v out - v set requirements specified in equation 14: out pin leakage current when the voltage on the out pin is greater than 10v, there is a leakage current flowing into the pin in addition to the i set current. figure 9 shows the i set current and the out pin current for out pin voltage up to 19v. in applications where the voltage on the out pin will be greater than 10v, the actual output voltage will be lower than the voltage calculated by equation 6. the graph in figure 9 was measured with r set = 4.99k . power supply sequence the recommended power supply sequencing is shown in figure 10. when applying power, v dd should be applied before or at the same time as a vdd . the minimum time for t vs is 0s. when removing power, the sequence of v dd and a vdd is not important. do not remove v dd or a vdd within 100ms of the start of the eeprom programming cycle. removing power before the eeprom programming cycle is completed may result in corrupted data in the eeprom. operating and programming supply voltage and current to program the eeprom, a vdd must be 10.8v. if programming is not required, the ISL24201 will operate over an a vdd range of 4.5v to 19v. during eeprom programming, i dd and i avdd will temporarily be higher than their quiescent curre nts. figure 11 shows a typical i dd and i avdd current profile during eeprom programming. the current pulses are erase and write cycles. the eeprom programming algorithm is shown in figure 12. the algorithm allows up to 4 erase cycles and 4 programming cycles, however typical parts only require 1 cycle of each, sometimes 2 when a vdd is near the minimum 10.8v limit. table 1. example v out vs register value register value v out (v) 08.49 20 8.34 40 8.18 60 8.02 80 7.87 100 7.71 120 7.55 127 7.50 140 7.40 160 7.24 180 7.09 200 6.93 220 6.77 240 6.62 255 6.50 v out min 6.5v 15v 20 ---------- > 0.3v + 1.05v == (eq. 14) 0.000 0.050 0.100 0.150 0.200 0.250 0.300 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 out pin voltage (v) out and set pin current vs. out pin voltage register = 255 out pin current set pin current current (ma) figure 9. out pin leakage current v dd a vdd t vs figure 10. power supply sequence
ISL24201 9 fn7586.1 december 9, 2010 ISL24201 programming the ISL24201 accepts i 2 c bus address and data when the wp pin is at or above v ih (>0.7v dd ). the ISL24201 ignores the i 2 c bus when the wp pin is at or below v il (<0.3v dd ). figure 13 shows the serial data format for writing the register and programming the eeprom. figure 14 shows the serial data format for reading the dac register. table 2 shows the truth table for reading and writing the device. programming the eeprom memory transfers the current dac register value to the eeprom and occurs when the control bits select the programming mode and the a vdd voltage is >10.8v. after the eeprom programming cycle is started, the wp pin can be returned to logic low while the while it completes, which takes a maximum of 100ms. the ISL24201 uses a 6 bit i 2 c address, which is ?100111xx?. the complete read and write protocol is shown in figures 13 and 14. i 2 c bus signals the ISL24201 uses fixed voltages for its i 2 c thresholds, rather than the percentage of v dd described in the i 2 c specification (see table 3). this should not ca use a problem in most systems, but the i 2 c logic levels in a specific design should be checked to ensure they are compatible with the ISL24201. vdd programming current ~1ms iavdd programming current i p 100ms max 2.7ma 200a 50a 90a 25a figure 11. i dd and i avdd current profile during eeprom programming figure 12. eeprom programming flowchart erase pulse start eeprom programming are eeprom cells erased? no yes w rite p ulse are eeprom cells programmed? eeprom programming complete no yes table 2. ISL24201 read and write control wp pin i 2 c bits function r/w program 0 1 x read register. 0 0 1 will acknowledge i 2 c transactions. will not write to register 0 0 0 will acknowledge i 2 c transactions. will not write to eeprom. 1 1 x read dac register 101write dac register 100 program eeprom table 3. ISL24201 i 2 c bus logic levels symbol ISL24201 i 2 c standard i 2 cv il 0.55v 0.3*v dd i 2 cv ih 1.44v 0.7*v dd
ISL24201 10 fn7586.1 december 9, 2010 i 2 c read and write format figure 13. i 2 c write format 6 bit address start r/w ack data program ack data lsb stop 10 01 1 1 0 d0 d7 d6 d5 d4 d3 d2 d1 p a a ISL24201 i 2 c write r/w = 0 = write r/w = 1 = read when r/w = 0 p = 0 = eeprom programming p = 1 = register w rite byte 1 byte 2 msb lsb msb lsb figure 14. i 2 c read format 6 bit address start r/w ack data ack x stop 10 011 1 1 x d7 d6 d5 d4 d3 d2 d1 a a ISL24201 i 2 c read r/w = 0 = write r/w = 1 = read d0 start byte 1 byte 2 msb lsb msb lsb
ISL24201 11 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7586.1 december 9, 2010 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: ISL24201 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/sear revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change 12/9/10 fn7586.1 on page 5, corrected min sp ec for ?tbuf? from 125s to 200s. 12/1/10 fn7586.0 initial release.
ISL24201 12 fn7586.1 december 9, 2010 package outline drawing l8.3x3a 8 lead thin dual flat no-lead plastic package rev 4, 2/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.20mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing c onform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view c 0 . 2 ref 0 . 05 max. 0 . 02 nom. 5 3.00 a b 3.00 (4x) 0.15 6 pin 1 index area pin #1 6x 0.65 1.50 0.10 8 1 8x 0.30 0.10 6 0.75 0.05 see detail "x" 0.08 0.10 c c c ( 2.90 ) (1.50) ( 8 x 0.30) ( 8x 0.50) ( 2.30) ( 1.95) 2.30 0.10 0.10 8x 0.30 0.05 a mc b 4 2x 1.950 (6x 0.65) index area pin 1 compliant to jedec mo-229 weec-2 except for the foot length. 7.

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